Kód: 01566042
This book presents a formal model for evaluating the cost effectiveness of computer architectures. The model can cope with a wide range of architectures, from CPU design to parallel supercomputers. To illustrate the formal procedu ... celý popis
Angličtina
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Anotace knihy
This book presents a formal model for evaluating the cost effectiveness of computer architectures. The model can cope with a wide range of architectures, from CPU design to parallel supercomputers. To illustrate the formal procedure of trade-off analyses, several non-pipelined design alternatives for the well-known RISC architecture called DLX are analyzed quantitatively. It is formally proved that the interrupt mechanism proposed for the DLX architecture handles nested interrupts correctly.In an appendix all programs to compute the cost and cycle time of the designs described are listed in C code. Running these simple C programs on a PC is sufficient to verify the results presented. The book addresses design professionals and students in computer architecture.
Parametry knihy
Zařazení knihy Knihy v angličtině Computing & information technology Computer science Computer architecture & logic design
1182 Kč
Angličtina
Osobní odběr Praha, Brno a 46010 dalších
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