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Anotace knihy

This book serves as a comprehensive guide, enabling readers to reap the full benefits of assertion-based verification, thereby minimizing hardware verification cost. Detailed descriptions of the SystemVerilog Assertions (SVA) language features are provided throughout the book, along with step-by-step examples of how they can be used to construct powerful sets of property checkers. This second edition includes a description of features introduced by the recent IEEE 1800-2012 SystemVerilog standard, explaining in detail the enhanced assertion constructs of the language, making it usable and accessible for designers, verification engineers, and EDA tool developers.

Parametry knihy

Zařazení knihy Knihy v angličtině Technology, engineering, agriculture Electronics & communications engineering Electronics engineering

• Plný název: SVA: The Power of Assertions in SystemVerilog
• Autor: Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny
• Jazyk: Angličtina
• Vazba: Pevná
• Počet stran: 590
• EAN: 9783319071381
• ISBN: 3319071386
• ID: 02667801
• Nakladatelství: Springer International Publishing AG
• Hmotnost: 1050 g
• Rozměry: 242 × 163 × 38 mm
• Datum vydání: 24. August 2014

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