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Více informací o knize Writing Testbenches: Functional Verification of HDL Models

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Anotace knihy

The Second Edition of Writing Testbenches, Functional Verification of HDL Models presents the latest verification techniques to produce fully functional first silicon ASICs, systems-on-a-chip (SoC), boards and entire systems.§Topics included in the new Second Edition: §Discussions on OpenVera and e; §Approaches for writing constrainable random stimulus generators; §Strategies for making testbenches self-checking; §A clear blueprint of a verification process that aims for first time success; §Recent advances in functional verification such as coverage-driven verification process; §VHDL and Verilog language semantics; §The semantics are presented in new verification-oriented languages;§Techniques for applying stimulus and monitoring the response of a design; §Behavioral modeling using non-synthesizeable constructs and coding style; §Updated for Verilog 2001. §

Parametry knihy

Zařazení knihy Knihy v angličtině Technology, engineering, agriculture Electronics & communications engineering Electronics engineering

• Plný název: Writing Testbenches: Functional Verification of HDL Models
• Autor: Janick Bergeron
• Jazyk: Angličtina
• Vazba: Brožovaná
• Počet stran: 478
• EAN: 9781461350125
• ISBN: 1461350123
• ID: 02180463
• Nakladatelství: Springer-Verlag New York Inc.
• Hmotnost: 777 g
• Rozměry: 235 × 155 × 28 mm
• Datum vydání: 21. October 2012

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