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Více informací o knize SATH: Simulated Annealing C code To FPGA Hardware compiler

• Parametry knihy
• Anotace
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Anotace knihy

A tool flow is presented for deriving accelerator§circuits on an FPGA §from ANSI C source code by exploring architecture§solutions that §conform to a preset template through scheduling and§mapping §algorithms. A case study carried out on simulated§annealing-based §scheduling software used for spacecraft systems is§explained. The goal §of the tool is the derivation of a design that§maximizes throughput §while minimizing footprint. Results obtained are§compared with a peer §C to RTL tool, a space-borne embedded processor and a§commodity§desktop processor for a variety of problems.

Parametry knihy

• Plný název: SATH: Simulated Annealing C code To FPGA Hardware compiler
• Podnázev: Customizing Pipelined Simulated Annealing IP cores with a dedicated C to FPGA compiler
• Autor: Jonathan Phillips
• Jazyk: Angličtina
• Vazba: Brožovaná
• Počet stran: 132
• EAN: 9783639165128
• ID: 06824904
• Nakladatelství: VDM Verlag Dr. Müller
• Hmotnost: 213 g
• Rozměry: 220 × 150 × 8 mm
• Rok vydání: 2009

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