Mohlo by se vám také líbit

Více informací o knize Logic Synthesis and SOC Prototyping

• Parametry knihy
• Anotace
• Oblíbené z jiného soudku

Nákupem získáte 267 bodů

Anotace knihy

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.

Parametry knihy

Zařazení knihy Knihy v angličtině Technology, engineering, agriculture Electronics & communications engineering Electronics engineering

• Plný název: Logic Synthesis and SOC Prototyping
• Podnázev: RTL Design using VHDL
• Autor: Vaibbhav Taraate
• Jazyk: Angličtina
• Vazba: Pevná
• Počet stran: 251
• EAN: 9789811513138
• ID: 24843032
• Nakladatelství: Springer, Berlin
• Hmotnost: 680 g
• Rozměry: 235 × 155 × 19 mm
• Datum vydání: 30. January 2020

Oblíbené z jiného soudku

---

---

---