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Více informací o knize Generating Hardware Assertion Checkers

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Anotace knihy

Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity.§This is the first book that presents an under-the-hood view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement.

Parametry knihy

Zařazení knihy Knihy v angličtině Computing & information technology Computer science

• Plný název: Generating Hardware Assertion Checkers
• Podnázev: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
• Autor: Marc Boule, Zeljko Zilic
• Jazyk: Angličtina
• Vazba: Pevná
• Počet stran: 280
• EAN: 9781402085857
• ISBN: 1402085850
• ID: 01418451
• Nakladatelství: Springer-Verlag New York Inc.
• Hmotnost: 1320 g
• Rozměry: 235 × 155 × 21 mm
• Datum vydání: 06. June 2008

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