Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design / Nejlevnější knihy
Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design

Kód: 14277562

Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design

Autor Weiwei Chen

This book offers readers a set of new approaches and tools a set of tools and techniques for facing challenges in parallelization with design of embedded systems. It provides an advanced parallel simulation infrastructure for effi ... celý popis

3313


Skladem u dodavatele v malém množství
Odesíláme za 12-15 dnů

Potřebujete více kusů?Máte-li zájem o více kusů, prověřte, prosím, nejprve dostupnost titulu na naši zákaznické podpoře.


Přidat mezi přání

Mohlo by se vám také líbit

Dárkový poukaz: Radost zaručena

Objednat dárkový poukazVíce informací

Více informací o knize Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design

Nákupem získáte 331 bodů

Anotace knihy

This book offers readers a set of new approaches and tools a set of tools and techniques for facing challenges in parallelization with design of embedded systems. It provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development so as to build better products in less time. Since parallel discrete event simulation (PDES) has the potential to exploit the underlying parallel computational capability in today's multi-core simulation hosts, the author begins by reviewing the parallelization of discrete event simulation, identifying problems and solutions. She then describes out-of-order parallel discrete event simulation (OoO PDES), a novel approach for efficient validation of system-level designs by aggressively exploiting the parallel capabilities of todays' multi-core PCs. This approach enables readers to design simulators that can fully exploit the parallel processing capability of the multi-core system to achieve fast speed simulation, without loss of simulation and timing accuracy. Based on this parallel simulation infrastructure, the author further describes automatic approaches that help the designer quickly to narrow down the debugging targets in faulty ESL models with parallelism.

Parametry knihy

Zařazení knihy Knihy v angličtině Technology, engineering, agriculture Electronics & communications engineering Electronics engineering

3313

Oblíbené z jiného soudku



Osobní odběr Praha, Brno a 12903 dalších

Copyright ©2008-24 nejlevnejsi-knihy.cz Všechna práva vyhrazenaSoukromíCookies


Můj účet: Přihlásit se
Všechny knihy světa na jednom místě. Navíc za skvělé ceny.

Nákupní košík ( prázdný )

Vyzvednutí v Zásilkovně
zdarma nad 1 499 Kč.

Nacházíte se: