Mohlo by se vám také líbit

Více informací o knize ASIC Design and Synthesis

• Parametry knihy
• Anotace
• Oblíbené z jiného soudku

Nákupem získáte 420 bodů

Anotace knihy

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

Parametry knihy

Zařazení knihy Knihy v angličtině Technology, engineering, agriculture Electronics & communications engineering Electronics engineering

• Plný název: ASIC Design and Synthesis
• Podnázev: RTL Design Using Verilog
• Autor: Vaibbhav Taraate
• Jazyk: Angličtina
• Vazba: Brožovaná
• Počet stran: 330
• EAN: 9789813346444
• ID: 38574120
• Nakladatelství: Springer Verlag, Singapore
• Hmotnost: 539 g
• Rozměry: 235 × 155 × 20 mm
• Datum vydání: 08. January 2022

Oblíbené z jiného soudku

---

---

---